Re: Fix for Bug 19851 (try 3) - Interlocked instruction support for ARM

[Alexandre Julliard]

Colin Fowler <elethiomel(a)gmail.com> writes:
> @@ -396,6 +396,88 @@
>                    "beq   $1,L0xchg_add\n\t"
>                    "mb")
>
> +
> +#elif defined(__arm__)
> +
> +/* 
> + * Similar to the Sparc, many ARM CPUs lack the necessary 
> + * atomic instructions. Fall back in a similar way, but instead
> + * use pthreads. This solution is generic enough to work on 
> + * pretty much any CPU, but is still very fast thanks to 
> + * Linux's NPTLS.
> + */

Actually since it's generic there's no reason to put it in an __arm__
ifdef, it could simply be the default fallback.

-- 
Alexandre Julliard
julliard(a)winehq.org

Fix for Bug 19851 (try 3) - Interlocked instruction support for ARM

[Colin Fowler]

I've only tested on ARM and wasn't comfortable enabling it for all other 
architectures (although I too see no reason why it wouldn't work).

Colin

Alexandre Julliard wrote:
> Colin Fowler <elethiomel(a)gmail.com> writes:
> > @@ -396,6 +396,88 @@
> >                    "beq   $1,L0xchg_add\n\t"
> >                    "mb")
> >
> > +
> > +#elif defined(__arm__)
> > +
> > +/* 
> > + * Similar to the Sparc, many ARM CPUs lack the necessary 
> > + * atomic instructions. Fall back in a similar way, but instead
> > + * use pthreads. This solution is generic enough to work on 
> > + * pretty much any CPU, but is still very fast thanks to 
> > + * Linux's NPTLS.
> > + */
>
> Actually since it's generic there's no reason to put it in an __arm__
> ifdef, it could simply be the default fallback.