http://bugs.winehq.org/show_bug.cgi?id=19982
--- Comment #32 from ray@pobox.co.uk 2009-09-30 15:53:18 --- (In reply to comment #22) I have also just spotted another very obscure bug:
proc_affinity = (1 << si.dwNumberOfProcessors) - 1;
This will typically generate:
00474CBD push 1 00474CBF pop eax 00474CC0 mov ecx,esi 00474CC2 shl eax,cl 00474CC4 dec eax
which for the case of 32 CPUs the after the shl eax,cl EAX will still contain 1 !
If you look in http://www.intel.com/Assets/PDF/manual/253667.pdf you will find:
IA-32 Architecture Compatibility The 8086 does not mask the shift count. However, all other IA-32 processors (starting with the Intel 286 processor) do mask the shift count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes (including the virtual-8086 mode) to reduce the maximum execution time of the instructions.