I suspect this MR will need a rebase in any case.
+ /* The HLSL docs state: "If components of a mad instruction are tagged as precise, the + * hardware must execute a mad instruction or the exact equivalent, and it cannot split + * it into a multiply followed by an add." + * But DXIL.rst states the opposite: "Floating point multiply & add. This operation is + * not fused for "precise" operations." + * Windows drivers seem to conform with the latter, for SM 4-5 and SM 6. */
The comment seems a bit unfortunate/ambiguous. The "HLSL docs" here refer to the "Shader Model 5 Assembly" documentation. (As opposed to e.g. referring to the translation of the HLSL mad() intrinsic to d3dbc/tpf.)
Do we want to handle this in the SPIR-V backend? It seems like something vsir_program_normalise() could take care of, possibly as part of the current vsir_program_lower_texkills() pass.