From: Francisco Casas fcasas@codeweavers.com
--- libs/vkd3d-shader/tpf.c | 114 +++++++++++++++++----------------------- 1 file changed, 49 insertions(+), 65 deletions(-)
diff --git a/libs/vkd3d-shader/tpf.c b/libs/vkd3d-shader/tpf.c index 049ca790..264bb0eb 100644 --- a/libs/vkd3d-shader/tpf.c +++ b/libs/vkd3d-shader/tpf.c @@ -1483,6 +1483,7 @@ struct vkd3d_sm4_register_type_info { enum vkd3d_sm4_register_type sm4_type; enum vkd3d_shader_register_type vkd3d_type; + enum vkd3d_sm4_dimension default_dimension; };
static const enum vkd3d_shader_register_precision register_precision_table[] = @@ -1522,42 +1523,42 @@ static void init_sm4_lookup_tables(struct vkd3d_sm4_lookup_tables *lookup)
static const struct vkd3d_sm4_register_type_info register_type_table[] = { - {VKD3D_SM4_RT_TEMP, VKD3DSPR_TEMP}, - {VKD3D_SM4_RT_INPUT, VKD3DSPR_INPUT}, - {VKD3D_SM4_RT_OUTPUT, VKD3DSPR_OUTPUT}, - {VKD3D_SM4_RT_INDEXABLE_TEMP, VKD3DSPR_IDXTEMP}, - {VKD3D_SM4_RT_IMMCONST, VKD3DSPR_IMMCONST}, - {VKD3D_SM4_RT_IMMCONST64, VKD3DSPR_IMMCONST64}, - {VKD3D_SM4_RT_SAMPLER, VKD3DSPR_SAMPLER}, - {VKD3D_SM4_RT_RESOURCE, VKD3DSPR_RESOURCE}, - {VKD3D_SM4_RT_CONSTBUFFER, VKD3DSPR_CONSTBUFFER}, - {VKD3D_SM4_RT_IMMCONSTBUFFER, VKD3DSPR_IMMCONSTBUFFER}, - {VKD3D_SM4_RT_PRIMID, VKD3DSPR_PRIMID}, - {VKD3D_SM4_RT_DEPTHOUT, VKD3DSPR_DEPTHOUT}, - {VKD3D_SM4_RT_NULL, VKD3DSPR_NULL}, - {VKD3D_SM4_RT_RASTERIZER, VKD3DSPR_RASTERIZER}, - {VKD3D_SM4_RT_OMASK, VKD3DSPR_SAMPLEMASK}, - {VKD3D_SM5_RT_STREAM, VKD3DSPR_STREAM}, - {VKD3D_SM5_RT_FUNCTION_BODY, VKD3DSPR_FUNCTIONBODY}, - {VKD3D_SM5_RT_FUNCTION_POINTER, VKD3DSPR_FUNCTIONPOINTER}, - {VKD3D_SM5_RT_OUTPUT_CONTROL_POINT_ID, VKD3DSPR_OUTPOINTID}, - {VKD3D_SM5_RT_FORK_INSTANCE_ID, VKD3DSPR_FORKINSTID}, - {VKD3D_SM5_RT_JOIN_INSTANCE_ID, VKD3DSPR_JOININSTID}, - {VKD3D_SM5_RT_INPUT_CONTROL_POINT, VKD3DSPR_INCONTROLPOINT}, - {VKD3D_SM5_RT_OUTPUT_CONTROL_POINT, VKD3DSPR_OUTCONTROLPOINT}, - {VKD3D_SM5_RT_PATCH_CONSTANT_DATA, VKD3DSPR_PATCHCONST}, - {VKD3D_SM5_RT_DOMAIN_LOCATION, VKD3DSPR_TESSCOORD}, - {VKD3D_SM5_RT_UAV, VKD3DSPR_UAV}, - {VKD3D_SM5_RT_SHARED_MEMORY, VKD3DSPR_GROUPSHAREDMEM}, - {VKD3D_SM5_RT_THREAD_ID, VKD3DSPR_THREADID}, - {VKD3D_SM5_RT_THREAD_GROUP_ID, VKD3DSPR_THREADGROUPID}, - {VKD3D_SM5_RT_LOCAL_THREAD_ID, VKD3DSPR_LOCALTHREADID}, - {VKD3D_SM5_RT_COVERAGE, VKD3DSPR_COVERAGE}, - {VKD3D_SM5_RT_LOCAL_THREAD_INDEX, VKD3DSPR_LOCALTHREADINDEX}, - {VKD3D_SM5_RT_GS_INSTANCE_ID, VKD3DSPR_GSINSTID}, - {VKD3D_SM5_RT_DEPTHOUT_GREATER_EQUAL, VKD3DSPR_DEPTHOUTGE}, - {VKD3D_SM5_RT_DEPTHOUT_LESS_EQUAL, VKD3DSPR_DEPTHOUTLE}, - {VKD3D_SM5_RT_OUTPUT_STENCIL_REF, VKD3DSPR_OUTSTENCILREF}, + {VKD3D_SM4_RT_TEMP, VKD3DSPR_TEMP, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_INPUT, VKD3DSPR_INPUT, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_OUTPUT, VKD3DSPR_OUTPUT, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_INDEXABLE_TEMP, VKD3DSPR_IDXTEMP, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_IMMCONST, VKD3DSPR_IMMCONST, 0}, + {VKD3D_SM4_RT_IMMCONST64, VKD3DSPR_IMMCONST64, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_SAMPLER, VKD3DSPR_SAMPLER, VKD3D_SM4_DIMENSION_NONE}, + {VKD3D_SM4_RT_RESOURCE, VKD3DSPR_RESOURCE, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_CONSTBUFFER, VKD3DSPR_CONSTBUFFER, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_IMMCONSTBUFFER, VKD3DSPR_IMMCONSTBUFFER, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_PRIMID, VKD3DSPR_PRIMID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_DEPTHOUT, VKD3DSPR_DEPTHOUT, VKD3D_SM4_DIMENSION_SCALAR}, + {VKD3D_SM4_RT_NULL, VKD3DSPR_NULL, VKD3D_SM4_DIMENSION_NONE}, + {VKD3D_SM4_RT_RASTERIZER, VKD3DSPR_RASTERIZER, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM4_RT_OMASK, VKD3DSPR_SAMPLEMASK, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_STREAM, VKD3DSPR_STREAM, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_FUNCTION_BODY, VKD3DSPR_FUNCTIONBODY, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_FUNCTION_POINTER, VKD3DSPR_FUNCTIONPOINTER, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_OUTPUT_CONTROL_POINT_ID, VKD3DSPR_OUTPOINTID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_FORK_INSTANCE_ID, VKD3DSPR_FORKINSTID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_JOIN_INSTANCE_ID, VKD3DSPR_JOININSTID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_INPUT_CONTROL_POINT, VKD3DSPR_INCONTROLPOINT, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_OUTPUT_CONTROL_POINT, VKD3DSPR_OUTCONTROLPOINT, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_PATCH_CONSTANT_DATA, VKD3DSPR_PATCHCONST, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_DOMAIN_LOCATION, VKD3DSPR_TESSCOORD, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_UAV, VKD3DSPR_UAV, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_SHARED_MEMORY, VKD3DSPR_GROUPSHAREDMEM, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_THREAD_ID, VKD3DSPR_THREADID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_THREAD_GROUP_ID, VKD3DSPR_THREADGROUPID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_LOCAL_THREAD_ID, VKD3DSPR_LOCALTHREADID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_COVERAGE, VKD3DSPR_COVERAGE, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_LOCAL_THREAD_INDEX, VKD3DSPR_LOCALTHREADINDEX,VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_GS_INSTANCE_ID, VKD3DSPR_GSINSTID, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_DEPTHOUT_GREATER_EQUAL, VKD3DSPR_DEPTHOUTGE, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_DEPTHOUT_LESS_EQUAL, VKD3DSPR_DEPTHOUTLE, VKD3D_SM4_DIMENSION_VEC4}, + {VKD3D_SM5_RT_OUTPUT_STENCIL_REF, VKD3DSPR_OUTSTENCILREF, VKD3D_SM4_DIMENSION_VEC4}, };
memset(lookup, 0, sizeof(*lookup)); @@ -3498,7 +3499,7 @@ struct sm4_register enum vkd3d_shader_register_type type; struct vkd3d_shader_register_index idx[2]; unsigned int idx_count; - enum vkd3d_sm4_dimension dim; + enum vkd3d_immconst_type immconst_type; uint32_t immconst_uint[4]; unsigned int mod; }; @@ -3545,7 +3546,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r if (regset == HLSL_REGSET_TEXTURES) { reg->type = VKD3DSPR_RESOURCE; - reg->dim = VKD3D_SM4_DIMENSION_VEC4; if (swizzle_type) *swizzle_type = VKD3D_SM4_SWIZZLE_VEC4; reg->idx[0].offset = var->regs[HLSL_REGSET_TEXTURES].id; @@ -3557,7 +3557,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r else if (regset == HLSL_REGSET_UAVS) { reg->type = VKD3DSPR_UAV; - reg->dim = VKD3D_SM4_DIMENSION_VEC4; if (swizzle_type) *swizzle_type = VKD3D_SM4_SWIZZLE_VEC4; reg->idx[0].offset = var->regs[HLSL_REGSET_UAVS].id; @@ -3569,7 +3568,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r else if (regset == HLSL_REGSET_SAMPLERS) { reg->type = VKD3DSPR_SAMPLER; - reg->dim = VKD3D_SM4_DIMENSION_NONE; if (swizzle_type) *swizzle_type = VKD3D_SM4_SWIZZLE_NONE; reg->idx[0].offset = var->regs[HLSL_REGSET_SAMPLERS].id; @@ -3584,7 +3582,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r
assert(data_type->class <= HLSL_CLASS_VECTOR); reg->type = VKD3DSPR_CONSTBUFFER; - reg->dim = VKD3D_SM4_DIMENSION_VEC4; if (swizzle_type) *swizzle_type = VKD3D_SM4_SWIZZLE_VEC4; reg->idx[0].offset = var->buffer->reg.id; @@ -3607,7 +3604,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r reg->idx_count = 1; }
- reg->dim = VKD3D_SM4_DIMENSION_VEC4; *writemask = ((1u << data_type->dimx) - 1) << (offset % 4); } else @@ -3616,7 +3612,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r
assert(hlsl_reg.allocated); reg->type = VKD3DSPR_INPUT; - reg->dim = VKD3D_SM4_DIMENSION_VEC4; if (swizzle_type) *swizzle_type = VKD3D_SM4_SWIZZLE_VEC4; reg->idx[0].offset = hlsl_reg.id; @@ -3638,10 +3633,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r reg->idx_count = 1; }
- if (reg->type == VKD3DSPR_DEPTHOUT) - reg->dim = VKD3D_SM4_DIMENSION_SCALAR; - else - reg->dim = VKD3D_SM4_DIMENSION_VEC4; *writemask = ((1u << data_type->dimx) - 1) << (offset % 4); } else @@ -3650,7 +3641,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r
assert(hlsl_reg.allocated); reg->type = VKD3DSPR_OUTPUT; - reg->dim = VKD3D_SM4_DIMENSION_VEC4; reg->idx[0].offset = hlsl_reg.id; reg->idx_count = 1; *writemask = hlsl_reg.writemask; @@ -3662,7 +3652,6 @@ static void sm4_register_from_deref(struct hlsl_ctx *ctx, struct sm4_register *r
assert(hlsl_reg.allocated); reg->type = VKD3DSPR_TEMP; - reg->dim = VKD3D_SM4_DIMENSION_VEC4; if (swizzle_type) *swizzle_type = VKD3D_SM4_SWIZZLE_VEC4; reg->idx[0].offset = hlsl_reg.id; @@ -3686,7 +3675,6 @@ static void sm4_register_from_node(struct sm4_register *reg, unsigned int *write { assert(instr->reg.allocated); reg->type = VKD3DSPR_TEMP; - reg->dim = VKD3D_SM4_DIMENSION_VEC4; *swizzle_type = VKD3D_SM4_SWIZZLE_VEC4; reg->idx[0].offset = instr->reg.id; reg->idx_count = 1; @@ -3707,14 +3695,14 @@ static void sm4_src_from_constant_value(struct sm4_src_register *src, src->reg.type = VKD3DSPR_IMMCONST; if (width == 1) { - src->reg.dim = VKD3D_SM4_DIMENSION_SCALAR; + src->reg.immconst_type = VKD3D_IMMCONST_SCALAR; src->reg.immconst_uint[0] = value->u[0].u; } else { unsigned int i, j = 0;
- src->reg.dim = VKD3D_SM4_DIMENSION_VEC4; + src->reg.immconst_type = VKD3D_IMMCONST_VEC4; for (i = 0; i < 4; ++i) { if (map_writemask & (1u << i)) @@ -3755,14 +3743,14 @@ static void sm4_write_dst_register(const struct tpf_writer *tpf, const struct sm { FIXME("Unhandled vkd3d-shader register type %#x.\n", dst->reg.type); sm4_reg_type = VKD3D_SM4_RT_TEMP; + reg_dim = VKD3D_SM4_DIMENSION_VEC4; } else { sm4_reg_type = register_type_info->sm4_type; + reg_dim = register_type_info->default_dimension; }
- reg_dim = dst->reg.dim; - token |= sm4_reg_type << VKD3D_SM4_REGISTER_TYPE_SHIFT; token |= dst->reg.idx_count << VKD3D_SM4_REGISTER_ORDER_SHIFT; token |= reg_dim << VKD3D_SM4_DIMENSION_SHIFT; @@ -3790,13 +3778,16 @@ static void sm4_write_src_register(const struct tpf_writer *tpf, const struct sm { FIXME("Unhandled vkd3d-shader register type %#x.\n", src->reg.type); sm4_reg_type = VKD3D_SM4_RT_TEMP; + reg_dim = VKD3D_SM4_DIMENSION_VEC4; } else { sm4_reg_type = register_type_info->sm4_type; + reg_dim = register_type_info->default_dimension; }
- reg_dim = src->reg.dim; + if (src->reg.type == VKD3DSPR_IMMCONST) + reg_dim = src->reg.immconst_type == VKD3D_IMMCONST_VEC4 ? VKD3D_SM4_DIMENSION_VEC4 : VKD3D_SM4_DIMENSION_SCALAR; if (src_info == 's') reg_dim = VKD3D_SM4_DIMENSION_VEC4;
@@ -3838,7 +3829,7 @@ static uint32_t sm4_register_order(const struct sm4_register *reg) { uint32_t order = 1; if (reg->type == VKD3DSPR_IMMCONST) - order += reg->dim == VKD3D_SM4_DIMENSION_VEC4 ? 4 : 1; + order += reg->immconst_type == VKD3D_IMMCONST_VEC4 ? 4 : 1; order += reg->idx_count; if (reg->mod) ++order; @@ -3921,7 +3912,6 @@ static void write_sm4_dcl_constant_buffer(const struct tpf_writer *tpf, const st { .opcode = VKD3D_SM4_OP_DCL_CONSTANT_BUFFER,
- .srcs[0].reg.dim = VKD3D_SM4_DIMENSION_VEC4, .srcs[0].reg.type = VKD3DSPR_CONSTBUFFER, .srcs[0].reg.idx[0].offset = cbuffer->reg.id, .srcs[0].reg.idx[1].offset = (cbuffer->used_size + 3) / 4, @@ -4029,7 +4019,6 @@ static void write_sm4_dcl_semantic(const struct tpf_writer *tpf, const struct hl
struct sm4_instruction instr = { - .dsts[0].reg.dim = VKD3D_SM4_DIMENSION_VEC4, .dst_count = 1, };
@@ -4054,9 +4043,6 @@ static void write_sm4_dcl_semantic(const struct tpf_writer *tpf, const struct hl instr.dsts[0].writemask = var->regs[HLSL_REGSET_NUMERIC].writemask; }
- if (instr.dsts[0].reg.type == VKD3DSPR_DEPTHOUT) - instr.dsts[0].reg.dim = VKD3D_SM4_DIMENSION_SCALAR; - hlsl_sm4_usage_from_semantic(tpf->ctx, &var->semantic, output, &usage); if (usage == ~0u) usage = D3D_NAME_UNDEFINED; @@ -4188,7 +4174,6 @@ static void write_sm4_unary_op_with_two_destinations(const struct tpf_writer *tp sm4_dst_from_node(&instr.dsts[dst_idx], dst); assert(1 - dst_idx >= 0); instr.dsts[1 - dst_idx].reg.type = VKD3DSPR_NULL; - instr.dsts[1 - dst_idx].reg.dim = VKD3D_SM4_DIMENSION_NONE; instr.dsts[1 - dst_idx].reg.idx_count = 0; instr.dst_count = 2;
@@ -4248,7 +4233,6 @@ static void write_sm4_binary_op_with_two_destinations(const struct tpf_writer *t sm4_dst_from_node(&instr.dsts[dst_idx], dst); assert(1 - dst_idx >= 0); instr.dsts[1 - dst_idx].reg.type = VKD3DSPR_NULL; - instr.dsts[1 - dst_idx].reg.dim = VKD3D_SM4_DIMENSION_NONE; instr.dsts[1 - dst_idx].reg.idx_count = 0; instr.dst_count = 2;
@@ -4320,7 +4304,7 @@ static void write_sm4_ld(const struct tpf_writer *tpf, const struct hlsl_ir_node memset(&instr.srcs[2], 0, sizeof(instr.srcs[2])); instr.srcs[2].swizzle_type = VKD3D_SM4_SWIZZLE_NONE; reg->type = VKD3DSPR_IMMCONST; - reg->dim = VKD3D_SM4_DIMENSION_SCALAR; + reg->immconst_type = VKD3D_IMMCONST_SCALAR; reg->immconst_uint[0] = index->value.u[0].u; } else if (tpf->ctx->profile->major_version == 4 && tpf->ctx->profile->minor_version == 0) @@ -4482,7 +4466,7 @@ static void write_sm4_cast_from_bool(const struct tpf_writer *tpf, const struct sm4_src_from_node(&instr.srcs[0], arg, instr.dsts[0].writemask); instr.srcs[1].swizzle_type = VKD3D_SM4_SWIZZLE_NONE; instr.srcs[1].reg.type = VKD3DSPR_IMMCONST; - instr.srcs[1].reg.dim = VKD3D_SM4_DIMENSION_SCALAR; + instr.srcs[1].reg.immconst_type = VKD3D_IMMCONST_SCALAR; instr.srcs[1].reg.immconst_uint[0] = mask; instr.src_count = 2;