On Wed Nov 8 13:44:26 2023 +0000, Giovanni Mascellani wrote:
So, it seems that the idea is that at any given time a VSIR program either has control flow based on `if`, `loop`, etc or based on `label` and `branch` (which are endowed with CFG structure information anyway). Is that true, or are cases in which the same program can legally have both types of instructions?
I expect it would work to have both and then pass it through the flattener, but it should not occur in practice.