Zebediah Figura : tests: Add more tests for UAV allocation.

[Alexandre Julliard]

Module: vkd3d
Branch: master
Commit: 8044fce040619235f69534441515c4ce68d1b5ba
URL:    https://gitlab.winehq.org/wine/vkd3d/-/commit/8044fce040619235f69534441515c4...

Author: Zebediah Figura 
Date:   Thu Oct 13 23:03:24 2022 -0500

tests: Add more tests for UAV allocation.

---

tests/uav.shader_test | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/tests/uav.shader_test b/tests/uav.shader_test
index 297cf14a..bc2fcb4d 100644
--- a/tests/uav.shader_test
+++ b/tests/uav.shader_test
@@ -22,6 +22,7 @@ float4 main() : sv_target
     return 0;
 }

+
 [uav 1]
 format r32 float
 size (2, 2)
@@ -54,3 +55,68 @@ probe uav 1 (0, 1) r (0.6)
 probe uav 1 (1, 0) r (0.2)
 probe uav 1 (1, 1) r (0.7)
 probe uav 2 (0, 0) rgba (2.0, 1.0, 4.0, 3.0)
+
+
+% UAVs are implicitly allocated starting from the highest render target slot.
+% They cannot overlap render target slots, and also cannot be allocated any
+% lower than the highest render target.
+% This ceases to be true with shader model 5.1.
+
+[render target 1]
+format r32g32b32a32 float
+size (640, 480)
+
+[uav 2]
+size (1, 1)
+
+0.1 0.2 0.3 0.4
+
+[pixel shader fail]
+RWTexture2D<float4> u : register(u0);
+
+float4 main() : sv_target1
+{
+    u[uint2(0, 0)] = float4(0.9, 0.8, 0.7, 0.6);
+    return 0;
+}
+
+[pixel shader fail]
+RWTexture2D<float4> u : register(u1);
+
+float4 main() : sv_target1
+{
+    u[uint2(0, 0)] = float4(0.9, 0.8, 0.7, 0.6);
+    return 0;
+}
+
+[pixel shader]
+RWTexture2D<float4> u;
+
+float4 main() : sv_target1
+{
+    u[uint2(0, 0)] = float4(0.9, 0.8, 0.7, 0.6);
+    return 0;
+}
+
+[test]
+todo draw quad
+probe uav 2 (0, 0) rgba (0.9, 0.8, 0.7, 0.6)
+
+
+[uav 3]
+size (1, 1)
+
+0.1 0.2 0.3 0.4
+
+[pixel shader]
+RWTexture2D<float4> u : register(u3);
+
+float4 main() : sv_target1
+{
+    u[uint2(0, 0)] = float4(0.9, 0.8, 0.7, 0.6);
+    return 0;
+}
+
+[test]
+todo draw quad
+probe uav 3 (0, 0) rgba (0.9, 0.8, 0.7, 0.6)