In order not to repeat the features, registers are expected to be ordered and grouped by feature. If feature name is set only on the first register of a new feature.
Signed-off-by: Rémi Bernon rbernon@codeweavers.com --- programs/winedbg/be_arm.c | 37 ++++----- programs/winedbg/be_arm64.c | 70 ++++++++--------- programs/winedbg/be_cpu.h | 1 + programs/winedbg/be_i386.c | 85 ++++++++++---------- programs/winedbg/be_ppc.c | 146 ++++++++++++++++++----------------- programs/winedbg/be_x86_64.c | 117 ++++++++++++++-------------- 6 files changed, 231 insertions(+), 225 deletions(-)
diff --git a/programs/winedbg/be_arm.c b/programs/winedbg/be_arm.c index ad0e2857cda2..afa0a4770cd6 100644 --- a/programs/winedbg/be_arm.c +++ b/programs/winedbg/be_arm.c @@ -1900,26 +1900,27 @@ static BOOL be_arm_set_context(HANDLE thread, const dbg_ctx_t *ctx) return SetThreadContext(thread, &ctx->ctx); }
-#define REG(r,gs) {FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs} +#define REG(f,r,gs) {f, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static struct gdb_register be_arm_gdb_register_map[] = { - REG(R0, 4), - REG(R1, 4), - REG(R2, 4), - REG(R3, 4), - REG(R4, 4), - REG(R5, 4), - REG(R6, 4), - REG(R7, 4), - REG(R8, 4), - REG(R9, 4), - REG(R10, 4), - REG(R11, 4), - REG(R12, 4), - REG(Sp, 4), - REG(Lr, 4), - REG(Pc, 4), - REG(Cpsr, 4), + REG("core", R0, 4), + REG(NULL, R1, 4), + REG(NULL, R2, 4), + REG(NULL, R3, 4), + REG(NULL, R4, 4), + REG(NULL, R5, 4), + REG(NULL, R6, 4), + REG(NULL, R7, 4), + REG(NULL, R8, 4), + REG(NULL, R9, 4), + REG(NULL, R10, 4), + REG(NULL, R11, 4), + REG(NULL, R12, 4), + REG(NULL, R13, 4), + REG(NULL, Sp, 4), + REG(NULL, Lr, 4), + REG(NULL, Pc, 4), + REG(NULL, Cpsr, 4), };
struct backend_cpu be_arm = diff --git a/programs/winedbg/be_arm64.c b/programs/winedbg/be_arm64.c index bca86b825740..7b856cd3d2b9 100644 --- a/programs/winedbg/be_arm64.c +++ b/programs/winedbg/be_arm64.c @@ -289,43 +289,43 @@ static BOOL be_arm64_set_context(HANDLE thread, const dbg_ctx_t *ctx) return SetThreadContext(thread, &ctx->ctx); }
-#define REG(r,gs) {FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs} +#define REG(f,r,gs) {f, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static struct gdb_register be_arm64_gdb_register_map[] = { - REG(Cpsr, 4), - REG(u.s.X0, 8), - REG(u.s.X1, 8), - REG(u.s.X2, 8), - REG(u.s.X3, 8), - REG(u.s.X4, 8), - REG(u.s.X5, 8), - REG(u.s.X6, 8), - REG(u.s.X7, 8), - REG(u.s.X8, 8), - REG(u.s.X9, 8), - REG(u.s.X10, 8), - REG(u.s.X11, 8), - REG(u.s.X12, 8), - REG(u.s.X13, 8), - REG(u.s.X14, 8), - REG(u.s.X15, 8), - REG(u.s.X16, 8), - REG(u.s.X17, 8), - REG(u.s.X18, 8), - REG(u.s.X19, 8), - REG(u.s.X20, 8), - REG(u.s.X21, 8), - REG(u.s.X22, 8), - REG(u.s.X23, 8), - REG(u.s.X24, 8), - REG(u.s.X25, 8), - REG(u.s.X26, 8), - REG(u.s.X27, 8), - REG(u.s.X28, 8), - REG(u.s.Fp, 8), - REG(u.s.Lr, 8), - REG(Sp, 8), - REG(Pc, 8), + REG("core", u.s.X0, 8), + REG(NULL, u.s.X1, 8), + REG(NULL, u.s.X2, 8), + REG(NULL, u.s.X3, 8), + REG(NULL, u.s.X4, 8), + REG(NULL, u.s.X5, 8), + REG(NULL, u.s.X6, 8), + REG(NULL, u.s.X7, 8), + REG(NULL, u.s.X8, 8), + REG(NULL, u.s.X9, 8), + REG(NULL, u.s.X10, 8), + REG(NULL, u.s.X11, 8), + REG(NULL, u.s.X12, 8), + REG(NULL, u.s.X13, 8), + REG(NULL, u.s.X14, 8), + REG(NULL, u.s.X15, 8), + REG(NULL, u.s.X16, 8), + REG(NULL, u.s.X17, 8), + REG(NULL, u.s.X18, 8), + REG(NULL, u.s.X19, 8), + REG(NULL, u.s.X20, 8), + REG(NULL, u.s.X21, 8), + REG(NULL, u.s.X22, 8), + REG(NULL, u.s.X23, 8), + REG(NULL, u.s.X24, 8), + REG(NULL, u.s.X25, 8), + REG(NULL, u.s.X26, 8), + REG(NULL, u.s.X27, 8), + REG(NULL, u.s.X28, 8), + REG(NULL, u.s.Fp, 8), + REG(NULL, u.s.Lr, 8), + REG(NULL, Sp, 8), + REG(NULL, Pc, 8), + REG(NULL, Cpsr, 4), };
struct backend_cpu be_arm64 = diff --git a/programs/winedbg/be_cpu.h b/programs/winedbg/be_cpu.h index ea559b44ba19..f6e712f8aa01 100644 --- a/programs/winedbg/be_cpu.h +++ b/programs/winedbg/be_cpu.h @@ -24,6 +24,7 @@ enum be_xpoint_type {be_xpoint_break, be_xpoint_watch_exec, be_xpoint_watch_read
struct gdb_register { + const char *feature; size_t ctx_offset; size_t ctx_length; size_t gdb_length; diff --git a/programs/winedbg/be_i386.c b/programs/winedbg/be_i386.c index 96562446eacf..cbe6ec3da299 100644 --- a/programs/winedbg/be_i386.c +++ b/programs/winedbg/be_i386.c @@ -865,50 +865,51 @@ static BOOL be_i386_set_context(HANDLE thread, const dbg_ctx_t *ctx) return Wow64SetThreadContext(thread, &ctx->x86); }
-#define REG(r,gs) {FIELD_OFFSET(WOW64_CONTEXT, r), sizeof(((WOW64_CONTEXT*)NULL)->r), gs} +#define REG(f,r,gs) {f, FIELD_OFFSET(WOW64_CONTEXT, r), sizeof(((WOW64_CONTEXT*)NULL)->r), gs}
static struct gdb_register be_i386_gdb_register_map[] = { - REG(Eax, 4), - REG(Ecx, 4), - REG(Edx, 4), - REG(Ebx, 4), - REG(Esp, 4), - REG(Ebp, 4), - REG(Esi, 4), - REG(Edi, 4), - REG(Eip, 4), - REG(EFlags, 4), - REG(SegCs, 4), - REG(SegSs, 4), - REG(SegDs, 4), - REG(SegEs, 4), - REG(SegFs, 4), - REG(SegGs, 4), - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[ 0]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[10]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[20]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[30]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[40]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[50]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[60]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[70]), 10, 10 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.ControlWord), 2, 4 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.StatusWord), 2, 4 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.TagWord), 2, 4 }, - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.ErrorSelector), 2, 4 }, - REG(FloatSave.ErrorOffset, 4 ), - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.DataSelector), 2, 4 }, - REG(FloatSave.DataOffset, 4 ), - { FIELD_OFFSET(WOW64_CONTEXT, FloatSave.ErrorSelector)+2, 2, 4 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[0]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[1]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[2]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[3]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[4]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[5]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[6]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[7]), 16, 16 }, - { FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, MxCsr), 4, 4 }, + REG("core", Eax, 4), + REG(NULL, Ecx, 4), + REG(NULL, Edx, 4), + REG(NULL, Ebx, 4), + REG(NULL, Esp, 4), + REG(NULL, Ebp, 4), + REG(NULL, Esi, 4), + REG(NULL, Edi, 4), + REG(NULL, Eip, 4), + REG(NULL, EFlags, 4), + REG(NULL, SegCs, 4), + REG(NULL, SegSs, 4), + REG(NULL, SegDs, 4), + REG(NULL, SegEs, 4), + REG(NULL, SegFs, 4), + REG(NULL, SegGs, 4), + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[ 0]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[10]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[20]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[30]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[40]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[50]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[60]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[70]), 10, 10}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.ControlWord), 2, 4}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.StatusWord), 2, 4}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.TagWord), 2, 4}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.ErrorSelector), 2, 4}, + REG(NULL, FloatSave.ErrorOffset, 4), + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.DataSelector), 2, 4}, + REG(NULL, FloatSave.DataOffset, 4), + { NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.ErrorSelector) + 2, 2, 4}, + + { "sse", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[0]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[1]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[2]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[3]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[4]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[5]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[6]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[7]), 16, 16}, + { NULL, FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, MxCsr), 4, 4}, };
struct backend_cpu be_i386 = diff --git a/programs/winedbg/be_ppc.c b/programs/winedbg/be_ppc.c index ff6ece6df3ae..5e49a3930d39 100644 --- a/programs/winedbg/be_ppc.c +++ b/programs/winedbg/be_ppc.c @@ -191,80 +191,82 @@ static BOOL be_ppc_set_context(HANDLE thread, const dbg_ctx_t *ctx) return SetThreadContext(thread, &ctx->ctx); }
-#define REG(r,gs,m) {FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs, m} +#define REG(f,r,gs) {f, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static struct gdb_register be_ppc_gdb_register_map[] = { - REG(Gpr0, 4), - REG(Gpr1, 4), - REG(Gpr2, 4), - REG(Gpr3, 4), - REG(Gpr4, 4), - REG(Gpr5, 4), - REG(Gpr6, 4), - REG(Gpr7, 4), - REG(Gpr8, 4), - REG(Gpr9, 4), - REG(Gpr10, 4), - REG(Gpr11, 4), - REG(Gpr12, 4), - REG(Gpr13, 4), - REG(Gpr14, 4), - REG(Gpr15, 4), - REG(Gpr16, 4), - REG(Gpr17, 4), - REG(Gpr18, 4), - REG(Gpr19, 4), - REG(Gpr20, 4), - REG(Gpr21, 4), - REG(Gpr22, 4), - REG(Gpr23, 4), - REG(Gpr24, 4), - REG(Gpr25, 4), - REG(Gpr26, 4), - REG(Gpr27, 4), - REG(Gpr28, 4), - REG(Gpr29, 4), - REG(Gpr30, 4), - REG(Gpr31, 4), - REG(Fpr0, 4), - REG(Fpr1, 4), - REG(Fpr2, 4), - REG(Fpr3, 4), - REG(Fpr4, 4), - REG(Fpr5, 4), - REG(Fpr6, 4), - REG(Fpr7, 4), - REG(Fpr8, 4), - REG(Fpr9, 4), - REG(Fpr10, 4), - REG(Fpr11, 4), - REG(Fpr12, 4), - REG(Fpr13, 4), - REG(Fpr14, 4), - REG(Fpr15, 4), - REG(Fpr16, 4), - REG(Fpr17, 4), - REG(Fpr18, 4), - REG(Fpr19, 4), - REG(Fpr20, 4), - REG(Fpr21, 4), - REG(Fpr22, 4), - REG(Fpr23, 4), - REG(Fpr24, 4), - REG(Fpr25, 4), - REG(Fpr26, 4), - REG(Fpr27, 4), - REG(Fpr28, 4), - REG(Fpr29, 4), - REG(Fpr30, 4), - REG(Fpr31, 4), - - REG(Iar, 4), - REG(Msr, 4), - REG(Cr, 4), - REG(Lr, 4), - REG(Ctr, 4), - REG(Xer, 4), + REG("core", Gpr0, 4), + REG(NULL, Gpr1, 4), + REG(NULL, Gpr2, 4), + REG(NULL, Gpr3, 4), + REG(NULL, Gpr4, 4), + REG(NULL, Gpr5, 4), + REG(NULL, Gpr6, 4), + REG(NULL, Gpr7, 4), + REG(NULL, Gpr8, 4), + REG(NULL, Gpr9, 4), + REG(NULL, Gpr10, 4), + REG(NULL, Gpr11, 4), + REG(NULL, Gpr12, 4), + REG(NULL, Gpr13, 4), + REG(NULL, Gpr14, 4), + REG(NULL, Gpr15, 4), + REG(NULL, Gpr16, 4), + REG(NULL, Gpr17, 4), + REG(NULL, Gpr18, 4), + REG(NULL, Gpr19, 4), + REG(NULL, Gpr20, 4), + REG(NULL, Gpr21, 4), + REG(NULL, Gpr22, 4), + REG(NULL, Gpr23, 4), + REG(NULL, Gpr24, 4), + REG(NULL, Gpr25, 4), + REG(NULL, Gpr26, 4), + REG(NULL, Gpr27, 4), + REG(NULL, Gpr28, 4), + REG(NULL, Gpr29, 4), + REG(NULL, Gpr30, 4), + REG(NULL, Gpr31, 4), + REG(NULL, Iar, 4), + REG(NULL, Msr, 4), + REG(NULL, Cr, 4), + REG(NULL, Lr, 4), + REG(NULL, Ctr, 4), + REG(NULL, Xer, 4), + + REG("fpu", Fpr0, 4), + REG(NULL, Fpr1, 4), + REG(NULL, Fpr2, 4), + REG(NULL, Fpr3, 4), + REG(NULL, Fpr4, 4), + REG(NULL, Fpr5, 4), + REG(NULL, Fpr6, 4), + REG(NULL, Fpr7, 4), + REG(NULL, Fpr8, 4), + REG(NULL, Fpr9, 4), + REG(NULL, Fpr10, 4), + REG(NULL, Fpr11, 4), + REG(NULL, Fpr12, 4), + REG(NULL, Fpr13, 4), + REG(NULL, Fpr14, 4), + REG(NULL, Fpr15, 4), + REG(NULL, Fpr16, 4), + REG(NULL, Fpr17, 4), + REG(NULL, Fpr18, 4), + REG(NULL, Fpr19, 4), + REG(NULL, Fpr20, 4), + REG(NULL, Fpr21, 4), + REG(NULL, Fpr22, 4), + REG(NULL, Fpr23, 4), + REG(NULL, Fpr24, 4), + REG(NULL, Fpr25, 4), + REG(NULL, Fpr26, 4), + REG(NULL, Fpr27, 4), + REG(NULL, Fpr28, 4), + REG(NULL, Fpr29, 4), + REG(NULL, Fpr30, 4), + REG(NULL, Fpr31, 4), + REG(NULL, Fpscr, 4), + /* FIXME: MQ is missing? FIELD_OFFSET(CONTEXT, Mq), */ /* see gdb/nlm/ppc.c */ }; diff --git a/programs/winedbg/be_x86_64.c b/programs/winedbg/be_x86_64.c index 83cbb3c05cee..22058ed15b0e 100644 --- a/programs/winedbg/be_x86_64.c +++ b/programs/winedbg/be_x86_64.c @@ -768,66 +768,67 @@ static BOOL be_x86_64_set_context(HANDLE thread, const dbg_ctx_t *ctx) return SetThreadContext(thread, &ctx->ctx); }
-#define REG(r,gs) {FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs} +#define REG(f,r,gs) {f, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs}
static struct gdb_register be_x86_64_gdb_register_map[] = { - REG(Rax, 8), - REG(Rbx, 8), - REG(Rcx, 8), - REG(Rdx, 8), - REG(Rsi, 8), - REG(Rdi, 8), - REG(Rbp, 8), - REG(Rsp, 8), - REG(R8, 8), - REG(R9, 8), - REG(R10, 8), - REG(R11, 8), - REG(R12, 8), - REG(R13, 8), - REG(R14, 8), - REG(R15, 8), - REG(Rip, 8), - REG(EFlags, 4), - REG(SegCs, 4), - REG(SegSs, 4), - REG(SegDs, 4), - REG(SegEs, 4), - REG(SegFs, 4), - REG(SegGs, 4), - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 0]), 10, 10 }, - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 1]), 10, 10 }, - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 2]), 10, 10 }, - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 3]), 10, 10 }, - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 4]), 10, 10 }, - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 5]), 10, 10 }, - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 6]), 10, 10 }, - { FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 7]), 10, 10 }, - REG(u.FltSave.ControlWord, 4), - REG(u.FltSave.StatusWord, 4), - REG(u.FltSave.TagWord, 4), - REG(u.FltSave.ErrorSelector, 4), - REG(u.FltSave.ErrorOffset, 4), - REG(u.FltSave.DataSelector, 4), - REG(u.FltSave.DataOffset, 4), - REG(u.FltSave.ErrorOpcode, 4), - REG(u.s.Xmm0, 16), - REG(u.s.Xmm1, 16), - REG(u.s.Xmm2, 16), - REG(u.s.Xmm3, 16), - REG(u.s.Xmm4, 16), - REG(u.s.Xmm5, 16), - REG(u.s.Xmm6, 16), - REG(u.s.Xmm7, 16), - REG(u.s.Xmm8, 16), - REG(u.s.Xmm9, 16), - REG(u.s.Xmm10, 16), - REG(u.s.Xmm11, 16), - REG(u.s.Xmm12, 16), - REG(u.s.Xmm13, 16), - REG(u.s.Xmm14, 16), - REG(u.s.Xmm15, 16), - REG(u.FltSave.MxCsr, 4), + REG("core", Rax, 8), + REG(NULL, Rbx, 8), + REG(NULL, Rcx, 8), + REG(NULL, Rdx, 8), + REG(NULL, Rsi, 8), + REG(NULL, Rdi, 8), + REG(NULL, Rbp, 8), + REG(NULL, Rsp, 8), + REG(NULL, R8, 8), + REG(NULL, R9, 8), + REG(NULL, R10, 8), + REG(NULL, R11, 8), + REG(NULL, R12, 8), + REG(NULL, R13, 8), + REG(NULL, R14, 8), + REG(NULL, R15, 8), + REG(NULL, Rip, 8), + REG(NULL, EFlags, 4), + REG(NULL, SegCs, 4), + REG(NULL, SegSs, 4), + REG(NULL, SegDs, 4), + REG(NULL, SegEs, 4), + REG(NULL, SegFs, 4), + REG(NULL, SegGs, 4), + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 0]), 10, 10}, + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 1]), 10, 10}, + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 2]), 10, 10}, + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 3]), 10, 10}, + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 4]), 10, 10}, + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 5]), 10, 10}, + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 6]), 10, 10}, + { NULL, FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[ 7]), 10, 10}, + REG(NULL, u.FltSave.ControlWord, 4), + REG(NULL, u.FltSave.StatusWord, 4), + REG(NULL, u.FltSave.TagWord, 4), + REG(NULL, u.FltSave.ErrorSelector, 4), + REG(NULL, u.FltSave.ErrorOffset, 4), + REG(NULL, u.FltSave.DataSelector, 4), + REG(NULL, u.FltSave.DataOffset, 4), + REG(NULL, u.FltSave.ErrorOpcode, 4), + + REG("sse", u.s.Xmm0, 16), + REG(NULL, u.s.Xmm1, 16), + REG(NULL, u.s.Xmm2, 16), + REG(NULL, u.s.Xmm3, 16), + REG(NULL, u.s.Xmm4, 16), + REG(NULL, u.s.Xmm5, 16), + REG(NULL, u.s.Xmm6, 16), + REG(NULL, u.s.Xmm7, 16), + REG(NULL, u.s.Xmm8, 16), + REG(NULL, u.s.Xmm9, 16), + REG(NULL, u.s.Xmm10, 16), + REG(NULL, u.s.Xmm11, 16), + REG(NULL, u.s.Xmm12, 16), + REG(NULL, u.s.Xmm13, 16), + REG(NULL, u.s.Xmm14, 16), + REG(NULL, u.s.Xmm15, 16), + REG(NULL, u.FltSave.MxCsr, 4), };
struct backend_cpu be_x86_64 =