On 20 Aug 2021, at 09:51, Henri Verbeet hverbeet@gmail.com wrote:
On Thu, 19 Aug 2021 at 10:56, Jan Sikorski jsikorski@codeweavers.com wrote:
We can generally skip them, but make sure that subsequent barriers synchronize with all accumulated usages.
Is that safe? I don't much doubt that this should work in practice on common desktop GPUs, but what does the spec say? In particular, I'd be a little concerned that e.g. VK_PIPELINE_STAGE_VERTEX_INPUT_BIT barriers may not guarantee visibility to e.g. fragment stages.
What scenario do you have in mind? You mean that we’d skip a barrier that would otherwise chain to some previous write? I think you're right, if I’m getting this right, a more clear example would maybe be a write to a read late in the pipeline (1st draw call), then to a read early in the pipeline (2nd draw call, this barrier would be skipped). The write would race with the second draw. Maybe the same would be true if the order of these draw calls was reversed. It would probably be preferable to sync with the write instead of the read to maintain parallelism.
- Jan